main.c
1 #include2 #include 3 4 #define uchar unsigned char 5 6 /***************************************************/ 7 #define TX_ADR_WIDTH 5 // 5字节宽度的发送/接收地址 8 #define TX_PLOAD_WIDTH 4 // 数据通道有效数据宽度 9 #define LED P2 10 11 uchar code TX_ADDRESS[TX_ADR_WIDTH] = { 0x34,0x43,0x10,0x10,0x01}; // 定义一个静态发送地址 12 uchar RX_BUF[TX_PLOAD_WIDTH]; 13 uchar TX_BUF[TX_PLOAD_WIDTH]; 14 uchar flag; 15 uchar DATA = 0x01; 16 uchar bdata sta; 17 sbit RX_DR = sta^6; 18 sbit TX_DS = sta^5; 19 sbit MAX_RT = sta^4; 20 21 22 /************************************************** 23 函数: init_io() 24 描述: 25 初始化IO 26 /**************************************************/ 27 void init_io(void) 28 { 29 CE = 0; // 待机 30 CSN = 1; // SPI禁止 31 SCK = 0; // SPI时钟置低 32 IRQ = 1; // 中断复位 33 LED = 0xff; // 关闭指示灯 34 } 35 36 /************************************************** 37 函数：delay_ms() 38 描述： 39 延迟x毫秒 40 /**************************************************/ 41 void delay_ms(uchar x) 42 { 43 uchar i, j; 44 i = 0; 45 for(i=0; i
1 // BYTE type definition 2 #ifndef _BYTE_DEF_ 3 #define _BYTE_DEF_ 4 typedef unsigned char BYTE; 5 #endif /* _BYTE_DEF_ */ 6 7 // Define interface to nRF24L01 8 #ifndef _SPI_PIN_DEF_ 9 #define _SPI_PIN_DEF_10 sbit CE = P1^2;11 sbit CSN= P1^3;12 sbit SCK= P1^1;13 sbit MOSI= P1^4;14 sbit MISO= P1^0;15 sbit IRQ = P1^5;16 #endif17 18 // Macro to read SPI Interrupt flag19 //#define WAIT_SPIF (!(SPI0CN & 0x80)) // SPI interrupt flag(礐 platform dependent)20 21 // Declare SW/HW SPI modes22 //#define SW_MODE 0x0023 //#define HW_MODE 0x0124 25 // Define nRF24L01 interrupt flag's26 //#define MAX_RT 0x10 // Max #of TX retrans interrupt27 //#define TX_DS 0x20 // TX data sent interrupt28 //#define RX_DR 0x40 // RX data received29 30 //#define SPI_CFG 0x40 // SPI Configuration register value31 //#define SPI_CTR 0x01 // SPI Control register values32 //#define SPI_CLK 0x00 // SYSCLK/2*(SPI_CLK+1) == > 12MHz / 2 = 6MHz33 //#define SPI0E 0x02 // SPI Enable in XBR0 register34 35 //****************************************************************//36 // SPI(nRF24L01) commands37 #define READ_REG 0x00 // Define read command to register38 #define WRITE_REG 0x20 // Define write command to register39 #define RD_RX_PLOAD 0x61 // Define RX payload register address40 #define WR_TX_PLOAD 0xA0 // Define TX payload register address41 #define FLUSH_TX 0xE1 // Define flush TX register command42 #define FLUSH_RX 0xE2 // Define flush RX register command43 #define REUSE_TX_PL 0xE3 // Define reuse TX payload register command44 #define NOP 0xFF // Define No Operation, might be used to read status register45 46 //***************************************************//47 // SPI(nRF24L01) registers(addresses)48 #define CONFIG 0x00 // 'Config' register address49 #define EN_AA 0x01 // 'Enable Auto Acknowledgment' register address50 #define EN_RXADDR 0x02 // 'Enabled RX addresses' register address51 #define SETUP_AW 0x03 // 'Setup address width' register address52 #define SETUP_RETR 0x04 // 'Setup Auto. Retrans' register address53 #define RF_CH 0x05 // 'RF channel' register address54 #define RF_SETUP 0x06 // 'RF setup' register address55 #define STATUS 0x07 // 'Status' register address56 #define OBSERVE_TX 0x08 // 'Observe TX' register address57 #define CD 0x09 // 'Carrier Detect' register address58 #define RX_ADDR_P0 0x0A // 'RX address pipe0' register address59 #define RX_ADDR_P1 0x0B // 'RX address pipe1' register address60 #define RX_ADDR_P2 0x0C // 'RX address pipe2' register address61 #define RX_ADDR_P3 0x0D // 'RX address pipe3' register address62 #define RX_ADDR_P4 0x0E // 'RX address pipe4' register address63 #define RX_ADDR_P5 0x0F // 'RX address pipe5' register address64 #define TX_ADDR 0x10 // 'TX address' register address65 #define RX_PW_P0 0x11 // 'RX payload width, pipe0' register address66 #define RX_PW_P1 0x12 // 'RX payload width, pipe1' register address67 #define RX_PW_P2 0x13 // 'RX payload width, pipe2' register address68 #define RX_PW_P3 0x14 // 'RX payload width, pipe3' register address69 #define RX_PW_P4 0x15 // 'RX payload width, pipe4' register address70 #define RX_PW_P5 0x16 // 'RX payload width, pipe5' register address71 #define FIFO_STATUS 0x17 // 'FIFO Status Register' register address72 73 //***************************************************************//74 // FUNCTION's PROTOTYPES //75 /****************************************************************76 void SPI_Init(BYTE Mode); // Init HW or SW SPI77 BYTE SPI_RW(BYTE byte); // Single SPI read/write78 BYTE SPI_Read(BYTE reg); // Read one byte from nRF24L0179 BYTE SPI_RW_Reg(BYTE reg, BYTE byte); // Write one byte to register 'reg'80 BYTE SPI_Write_Buf(BYTE reg, BYTE *pBuf, BYTE bytes); // Writes multiply bytes to one register81 BYTE SPI_Read_Buf(BYTE reg, BYTE *pBuf, BYTE bytes); // Read multiply bytes from one register82 //*****************************************************************/